In a typical Very Large Scale Integrated (VLSI) high-speed input-output (I/O) receiver (Rx) circuit, incoming data stream is sampled at an analog front-end (AFE) unit controlled by a 4-phase sampling clock signal (φ1-φ4) provided from a phase interpolator (PI). FIG. 1 is a typical AFE 100 which consists of an amplifying stage 101, a passive discrete-time linear equalizer (DTLE) 102, and a decision feedback equalizer (DFE) 103.
The AFE 100, however, suffers from bandwidth degradation due to multi-stage circuit architecture—the multiple stages being 101, 102, and 103. The AFE 100 being a multi-stage architecture also exhibits high power dissipation due to the presence of several active circuit stages. The power dissipation further increases when bias current to the analog circuits in the AFE 100 is increased to achieve higher bandwidth for Rx channels. The incoming data stream (Rx+ and Rx−) at the AFE 100 is effectively sampled inside the DFE/Sampler stage 103 which is physically far away from the Rx input ports near 101. This physical distance increases the chances of noise injection to the sampled signals and degrades the performance of the link.
The term “performance” herein generally refers to power supply rejection ratio (PSRR), power consumption, process-temperature-voltage (PVT) variations, area, scalability to lower power supply voltages, I/O transfer rate, etc.
The AFE 100 has many analog circuits requiring high precision analog voltage and current circuits for their operation. These analog circuits make the AFE 100 highly sensitive to process-voltage-temperature (PVT) variations and transistor device mismatch effects. The AFE 100, and similar AFEs, are unable to meet the stringent low power specifications of Mobile Industry Processor Interface (MIPI®) as described in the MIPI® Alliance Specification for M-PHYSM Version 1.00.00 of Feb. 8, 2011 and approved on Apr. 28, 2011.